1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly, to a semiconductor device improved to prevent reduction in drivability of an MOS transistor. The present invention also relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
FIG. 30 is an enlarged view showing a transistor portion of a conventional ASIC (Application Specific Integrated Circuit).
ASIC is an LSI manufactured for a special order from a specific user. An example of the ASCI includes a gate array LSI and a full custom design LSI.
Referring to FIG. 30, the conventional ASIC is provided with a silicon substrate 1. At a main surface of silicon substrate 1 is formed a field oxide film 4 for isolating an active region from another. On the active region is provided a gate electrode 6A of a two-layer structure including a refractory metal film 7A. Refractory metal film 7A is formed of, for example, tungsten silicide. A gate insulating film 5A is provided between silicon substrate 1 and gate electrode 6A. Source/drain regions of an LDD structure are provided on both sides of gate electrode 6A in the main surface of silicon substrate 1. The source/drain region consists of a low concentration N-type impurity diffusion layer (concentration of 1.times.10.sup.14 atoms/cm.sup.3 or more) 9A, 9B and a high concentration N-type impurity diffusion layer (concentration of 1.times.10.sup.16 atoms/cm.sup.3 or more) 10A, 10B. An outer edge of low concentration N-type impurity diffusion layer 9A, 9B extends under gate electrode 6A.
An interlayer insulating film 11 is provided on silicon substrate 1 so as to cover gate electrode 6A. In interlayer insulating film 11, a contact hole 12A for exposing a portion of a surface of high concentration N-type impurity diffusion layer 10A and a contact hole 12B for exposing a portion of a surface of high concentration N-type impurity diffusion layer 10B are provided. An aluminum interconnection 13A is connected to high concentration N-type impurity diffusion layer 10A through contact hole 12A. An aluminum interconnection 13B is connected to high concentration N-type impurity diffusion layer 10B through contact hole 12B. A passivation film 14 for protecting a surface is provide on silicon substrate 1 so as to cover aluminum interconnections 13A and 13B.
A method of manufacturing a semiconductor device shown in FIG. 30 will now be described.
Referring to FIG. 31, an underlying oxide film 2 is formed on silicon substrate 1 by thermal oxidation. A nitride film 3 is formed on underlying oxide film 2 by CVD (Chemical Vapor Deposition).
Referring to FIGS. 31 and 32, nitride film 3 is patterned by photolithography so as to make an opening in a portion where the field oxide film is formed.
Referring to FIGS. 32 and 33, field oxide film 4 is formed by selectively oxidating a surface of silicon substrate 1 using a pattern of nitride film 3 as a mask. The pattern of nitride film 3 is then removed (the above-described method is referred to as LOCOS).
Referring to FIGS. 33 and 34, underlying oxide film 2 is removed.
Referring to FIG. 35, a gate oxide film 5 having a thickness in the range of 100-200 .ANG. is formed on the surface of silicon substrate 1 by thermal oxidation.
Referring to FIG. 36, a polysilicon film 6 is formed on silicon substrate 1 by CVD. Refractory metal film 7 such as tungsten silicide is formed on polysilicon film 6 by sputtering.
Referring to FIGS. 36 and 37, polysilicon film 6 and refractory metal film 7 are patterned by photolithography to form gate electrode 6A of two-layer structure including refractory metal film 7A. Phosphorus ions are implanted to the surface of silicon substrate 1 (30-40 KeV, concentration in a range of 1.times.10.sup.13 -1.times.10.sup.14 atoms/cm.sup.2) using gate electrode 6A as a mask, whereby an impurity layer 9 which serves as a base of the low concentration N-type impurity diffusion layer is formed.
Referring to FIG. 38, an oxide film 8 is formed on silicon substrate 1 by CVD so as to cover gate electrode 6A.
Referring to FIGS. 38 and 39, oxide film 8 is etched by anisotropic etching to form a sidewall spacer 8A on a sidewall of gate electrode 6A. Arsenic ions are implanted to the surface of silicon substrate 1 (40-50 KeV, 1.times.10.sup.16 atom/cm.sup.2) using gate electrode 6A and sidewall spacer 8A as a mask to form an impurity layer 10 which serves as a base of the high concentration N-type impurity diffusion layer.
Referring to FIG. 40, low concentration N-type impurity regions 9A and 9B and high concentration N-type impurity regions 10A and 10B are formed on the main surface of silicon substrate 1 by thermal treatment. Interlayer insulating film 11 is formed on silicon substrate 1 so as to cover gate electrode 6A. In interlayer insulating film 11 are formed contact hole 12A for exposing a portion of the surface of high concentration N-type impurity region 10A and contact hole 12B for exposing a portion of the surface of high concentration N-type impurity region 10B. An aluminum/silicon film 13 is formed on silicon substrate 1 by sputtering so as to be connected to high concentration N-type impurity regions 10A and 10B through contact holes 12A and 12B. Referring to FIGS. 40 and 41, aluminum interconnections 13A and 13B are formed by selectively etching aluminum/silicon film 13 by photolithography. Passivation film 14 is formed on silicon substrate 1 so as to cover aluminum interconnections 13A and 13B.
Another prior art associated with the present invention will now be described.
FIGS. 42 and 43 are cross sections of a semiconductor device disclosed in Japanese Patent Laying-Open No. 4-112579.
Referring to FIG. 42, gate electrode 6A is provided on semiconductor substrate 1. A pair of source/drain regions 10A and 10B are formed on both sides of gate electrode 6A in the surface of semiconductor substrate 1. A gate oxide film 5A is provided between semiconductor substrate 1 and gate electrode 6A. Both side portions of gate oxide film 5A are thicker than the central portion thereof.
In the semiconductor device shown in FIG. 43, one of the side portions of gate oxide film 5A is thicker than the central portion thereof.
As described above, by making thick gate oxide film 5A thick near the peak portion of hot carrier implantation, aging effect on device characteristics can be prevented, resulting in a reliable MOS transistor.
The conventional semiconductor device configured as described has the following problems. That is, referring to FIG. 30, low concentration N-type impurity regions 9A and 9B overlap gate electrode 6A. Therefore, a parasitic capacitance (hereinafter referred to as gate overlap capacitance) is formed in which gate electrode 6A is one electrode and low concentration N-type impurity region 9A (9B) is the other electrode. As a result, charge and discharge of the parasitic capacitance occur, leading to reduction in drivability of the semiconductor device.
Also in the semiconductor device shown in FIGS. 42 and 43, source/drain regions 10A and 10B overlap gate electrode 6A. Therefore, the parasitic capacitance is formed in which gate electrode 6A is one electrode and source/drain region 10A, 10B is the other electrode.